Special-Purpose VLSI-Based System for the Analysis of 

 Genetic Sequences 



T. Hunkapiller, M. Waterman, R. Jones, M. Eggert, E. Chow, J. Peterson, and L. Hood 

 Department of Biology, California Institute of Technology, Pasadena, CA 91 125 



(818)356-6408 



The current size of genetic sequence databases means that extensive similarity analyses 

 based on robust mathematical models require large, expensive computer hardware not 

 generally available to most investigators. We are currently involved in developing a 

 hardware alternative — a VLSI-based system (i.e., very large scale integrated) — that will 

 give most laboratories access to these rigorous algorithms at the level of affordable 

 workstations and/or PCs. We are designing a board-level biological information signal 

 processor (BISP) coprocessor assembly. BISP is a systolic implementation of dynamic 

 programming methods for the determination of local sequence similarities and 

 alignments. Each BISP board will include an array of BISP processor chips responsible 

 for performing the dynamic programming methods and a tightly coupled coprocessor 

 (i860) that will provide complete alignments to the host central processing unit (CPU) 

 from the scoring information and locations provided by the systolic array. Difference 

 tables and gapping penalties are completely user-definable. Also, there are no arbitrary 

 limits on sequence lengths of either the query or database sequences, and searches can 

 be made simultaneously for multiple query sequences (depending on the size of the 

 sequences and the systolic array). The array will process at up to 20 megacharacters per 

 second. At this maximum speed, a query sequence the size of the systolic array could be 

 compared against all of the current GenBank® (both orientations) in under 3 s. The size 

 of the array is extensible and will range from about 500 processor cells to several 

 thousand. The BISP chip is being implemented in 1 mm cMOS technology, based on 

 custom standard cell methods. Each chip will have multiple identical processor cells, 

 local control circuits, and a results cache. The nearly full-custom processor cell design 

 is nearing completion, and the control circuit logic and floor plan have been generally 

 detailed. Our present schedule calls for tested design vectors to be completed by late fall 

 and handed over to the fabrication service for prototype chip delivery by winter 1990. 



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