SEMICONDUCTOR DIODE GATES 1147 



If the maximum signal generator current is chosen as 



7o = 5 10"' 



inequalities (11) and (13) take the form: 



h + 5 10~' Eb > 5.05 10"' 



-1.1 76 + 10-' Eb > 5.0 10"' 



No negative signal voltages were used, so inequality (12) is not involved. 

 The above inequalities limit h and Eb as shown in Fig. G. h and Eb 

 must be chosen from the shaded area. The values chosen were h = 5ma 

 and Eb = 15 volts. 



Comparing experimental results with analytic, gives: 



Voltage loss 1.0 db (computed 1.6 db) 

 Pedestal 5.05 volts (computed 5.45 volts) 



Further experimental results, which are all in reasonable agreement with 

 expectations are given on Figs. 7, 8 and 9. Fig. 7 shows how the pedestal 

 voltage varies with gate voltage (Eb). This is also a measure of the load 

 capacity, since the signal output can swing from zero to twice the pedes- 

 tal. The useful range is above the point where the pedestal ceases to 

 increase with gate voltage. In this range the control diode is cut off. 

 Figure 8 shows the pedestal against bias current /&. The limiting is not 

 as sharp here because the forward conductance of the input and output 



1.2 



5 10 



2 



j 



2 4 6 8 10 12 14 16 18 20 22 24 



Eb IN VOLTS 



Fig. 6 — Bias restrictions on transmission gate. 



