SEMICONDUCTOR DIODE GATES 



1149 



3.0 

 2.5 



5 1.0 

 o 



0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 6.0 

 BIAS MILLIAMPERES 



Fig. 8 — Transmission gate output (pedestal) potential versus bias current 

 magnitude. 



difficulty. One of the controls could instead be used as an inhibitor. For 

 example, if E2 were normally biased sufficiently positive it would have 

 no effect on the output, which would be controlled by Ei alone. How- 

 ever, a negative, or inhibiting pulse, sufficient to make D2 conducting, 

 would permit the bias current to flow in that path and prevent an out- 

 put, whatever the state of A- 



This circuit could be analyzed in exactly the same manner as was done 

 with the transmission gate. However, after a value of Rl has been chosen, 

 a simple first approximation to a design may be carried out by assuming 

 that the diodes are ideal, switching between zero and infinite resistance. 

 In choosing Rl there are three major considerations: 



1. Rl must be small compared with the reverse resistance of the diode, 

 D2, or there may be an appreciable negative output when the gate is 

 disabled. 



2. Rl must be large compared with the forward resistance of D3 for 

 efficient operation of the enabled gate, — preventing an appreciable 

 voltage loss due to the voltage drop in D3. 



3. The peak amplitude of the output pulse is IiRl- 



The value of Rl, which is chosen from the wide range of possibilities, 

 is a matter of practical compromise, depending on the impedance levels 

 in the system and the constant current generators which are available. 



Having chosen Rl and lb there remain only the control voltages, 

 El and E2. The voltages which are necessary to hold the gate enabled 

 can be obtained by noting that (in the ideal diode case) 



V.= V, = RlI 



Lift 



(19) 



To hold the control diodes non-conducting the voltages Ei and E^. 

 must be greater than Vb. This gives: 



