TRANSISTOR CIRCUITS FOR ANALOG AND DIGITAL SYSTEMS 313 



resistance summing network, a 400-cycle synchronous chopper, and a 

 tuned 400-cycle amplifier. Any drift in the summing amplifier will pro- 

 duce a dc voltage Es at the output of the summing network. The chopper 

 converts the dc voltage into a 400 cycles per second waveform. The 

 fundamental frequency in the waveform is amplified by a factor of about 

 400,000 by the tuned amplifier. The synchronous chopper rectifies the 

 sinusoidal output voltage and preserves the original dc polarity of Eg . 

 The rectified voltage is filtered and fed back to the summing amplifier 

 as an additional input current. The loop voltage gain of the AZS circuit 

 at dc is about 54 db. Any dc or low-frequency drift in the summing 

 amplifier is reduced by a factor of about 500 by the AZS circuit. The 

 drift throughout a temperature range of to 50°C is reduced to ±3 

 millivolts. 



Since the drift in the summing amplifier changes at a relatively slow 

 rate, the loop voltage gain of the AZS circuit can be cutoff at a relatively 

 low frequency. In this particular case the loop voltage gain is zero db at 

 about 10 cycles per second. 



4.0. THE INTEGRATOR 



4.1. Basic Design Considerations 



The design principles previously discussed are illustrated in this sec- 

 tion by the design of a transistor integrator for application in a voltage 



VvV 



-OUT 



Fig. 11 — DC summing amplifier with automatic zero set. 



