THE DESIGN OF TETRODE TRANSISTOR AMPLIFIERS 



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FREQUENCY IN MEGACYCLES PER SECOND 



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Fig. 18 — Measured and computed response of the stage shown on Fig. 17. 



An IF Amplifier Centered at 70 Mc. 



Although we do not have complete data on the parameter values of 

 tetrode transistors in this frequency range, amplifiers with a center fre- 

 quency of 70 mc have been built and their performance measured. The 

 amplifier was designed to provide a flat gain characteristic over the fre- 

 quency range from 60 to 80 mc. The stage was designed with the equiv- 

 alent of a double tuned transformer, interstage circuit with the trans- 

 former being replaced by the equivalent tee section. The selective circuit 

 is terminated at its output into the load resistance in the case of the last 

 stage or by the input impedance of the following transistor when it is 

 used as an interstage network. The impedance transformation of the 

 network is approximately 75 ohms to 1,500 ohms so it is essentially un- 

 terminated at the collector. By using a sweeping oscillator, such a stage 

 can be adjusted to result in a fairly flat frequency response. A typical 

 stage is shown on Fig. 19. The output terminals are connected to either 

 the load or the next emitter. The response obtained from a 3-stage am- 

 plifier is shown on Fig. 20. In order to determine the variation of gain 



