1076 THE BELL SYSTEM TECHNICAL JOURNAL, SEPTEMBER 1956 



are likewise widened to a corresponding width by blocking oscillator B. 

 Unfortunately a variable phase shift is introduced in the repeater output 

 by interference and by variations in the timing wave amplitude and 

 phase. This variable phase shift prevents perfect coincidence between 

 the outputs of blocking oscillators A and B. An example of phase "jitter" 

 caused by interference is shown on Plate V(a). To overcome this a 

 sharp sampling pip; as shown on the same plate, is provided to enable 

 the detection of the narrow region of coincidence between the two signals. 

 These pips are generated from the repeater timing wave, hence they 

 follow the timing wave phase variations. The regenerated signal pulses 

 also follow the timing wave phase. If the sampling pulse is positioned to 

 fall in the center of the regenerated pulses, it will tend to maintain that 

 position as the timing wave changes. 



The gates require a signal pulse and sampling pip to be present 

 simultaneously before there can be an output. This output, then, will 

 have substantially the same shape and position as the sampling pip. 

 When a signal pulse is simultaneously applied to each gate the two 

 outputs can be made to cancel when added in opposite phase as is done 

 in Ti . If however there is a pulse on one gate and a blank on the other, 

 an output pulse will be produced. The polarity of this pulse will depend 

 upon which gate contains the signal pulse. Since the decade counter is 



PULSE 



CODE 



GENERATOR 



■w-v 



DELAY 

 LINE 



BLOCKING 

 OSCILLATOR 



(A) 



V\AP 



AMPLIFIER 



DIFFEREN- 

 TIATOR 



iULJL 



"and" 



GATE 

 (A) 



VvV MAI 



SAMPLING 



BLOCKING 



OSCILLATOR 



BLOCKING 

 OSCILLATOR 



(B) 



J] n. 



"and" 



GATE 



(B) 



OMISSION ERROR 



OUTPUT TO CABLE 

 "AND NEXT REPEATER 



11_L 



TI 



JLJ_ 



POLARITY 



REVERSING 



SWITCH 



JL 



BLOCKING 



OSCILLATOR 



(D) 



JL 



DECADE 

 COUNTER 



Fig. 7 — Block diagram of error detecting circuit. 



