1108 THE BELL SYSTEM TECHNICAL JOURNAL, SEPTEMBER 1956 



R2, but the maximum value of R2 is limited by stray capacitance from 

 the transistor base to ground.* The average clock standby power for 

 this circuit (with a 10 volt peak clock voltage) is approximately 13 milli- 

 watts. The second part of the clock power occurs at turn-off when the 

 clock must supply approximately the full "on" state collector current. 

 In this design the clock supplies about 20 milliamperes of current for 0.1 

 microsecond at voltages up to about 6 volts peak before the transistor 

 turns off. Therefore, a negative resistance feedback circuit usually re- 

 quires a relatively large amount of standby clock power continuously 

 and a high peak clock power at turn-off. Also it should be noted that 

 diode Dl must have a short reverse recovery time in order to prevent 

 false triggering during the negative portion of the clock cycle. 



A second example of synchronization is shown in Fig. 11. Here the 

 clock signal is introduced in the feedback circuit to control turn-off. It 

 is also applied to R2 in the input circuit so as to control turn-on. In this 

 circuit most of the clock power is dissipated in R5 and R6 when the clock 

 voltage is positive during the output pulse time slot (whether or not an 

 output pulse is produced). Necessarily, this power is relatively large be- 

 cause the clock must supply the full amount of feedback current. Also, 

 it is necessary to clip the positive peak of the clock voltage in order to 

 prevent false triggering via R2 when there is no input pulse. A square 

 wave clock signal would eliminate the need for R6 and D7, but would 

 not change the power in R5. The average clock power in a typical circuit 

 of this type is approximately 20 milliwatts, which is relatively large. The 

 principal advantage of this method is that diode reverse recovery time 

 is not a problem. 



A third method of synchronization is to apply a square wave clock 

 signal (a sine wave is not suitable in this case) between the base of the 

 transistor and ground (for example, assume in Fig. 11 that R2 and 

 R5 are returned directly to V6 and that the base of the transistor is 

 the clock terminal instead of ground). Before turn-on the clock voltage 

 must be more positive than the trigger voltage on the emitter. At turn- 

 on the clock voltage drops rapidly to ground potential and triggering 

 takes place. During the pulse duration the base current of the transistor 

 is supplied by the clock source. At turn-off the clock voltage must rise 

 rapidly several volts until D6 conducts and robs current from the feed- 

 back loop. The clock power required by this method is relatively large 

 (order of 20 milliwatts) for point contact transistors because the base 

 current of such units is large. In a junction transistor with alpha close 



* The capacitance causes the base voltage to lag the clock voltage at turn-on 

 if R2 is large, which degrades the timing. 



