TRANSISTOR PULSE REGENERATIVE AMPLIFIERS 1109 



to unity the base current is small and the required clock power may be 

 as low as 3 milliwatts. However, it should be noted that this method of 

 synchronization applies only to amplifiers with a gated feedback circuit 

 (such as R5 and D6 in Fig. 11). In other circuits (Fig. 12, for example), 

 a clock voltage applied to the base terminal of the transistor may never 

 be able to turn off the transistor (the feedback current may actually 

 increase instead of decrease). Thus, this method of synchronization is 

 limited and is a low power method only when used with junction tran- 

 sistors. 



A fourth synchronization method, which avoids the limitations cited 

 in the previous examples, is illustrated in Fig. 12. The timing circuit 

 is simply diode Dl. The operation of the circuit, which is like an inhibit 

 logic circuit, is as follows. When trigger current commences, the clock 

 voltage is negative and Dl conducts the trigger current away from the 

 emitter terminal. As the clock voltage rises positiveward, the emitter 

 voltage follows until it reaches the threshold voltage of the transistor, 

 usually ground potential. Then the trigger current flows into the tran- 

 sistor which turns on. As the clock voltage continues positiveward the 

 emitter conduction clamps the emitter voltage so that Dl opens and the 

 clock does not shunt the feedback path during the pulse duration. At the 

 end of the pulse duration the clock voltage goes negativeward through 

 ground potential and Dl becomes conducting. This action robs current 

 from the feedback loop, thus causing the transistor to turn off. If no 

 input pulse is present, Dl is always non-conducting and any small re- 

 verse leakage current is drained off through El (which is returned to 

 voltage VI). 



Because diode Dl is always non-conducting when no input pulse is 

 present, the standby clock power is essentially zero. During a pulsing 

 cycle the clock conducts only a small current before turn-on and only 

 instantaneously at a low voltage at turn-off. Hence, the required clock 

 power is usually less than two milliwatts. 



It is important to note that the amplitude of the negative peak of the 

 clock voltage usually should not be more negative than the quiescent 

 bias voltage on the emitter. If it should be, Dl will conduct and, due to 

 minority carrier storage, may cause false triggering when the clock volt- 

 age goes positive. The current through Dl at turn-off might have the 

 same effect in the succeeding cycle except that the flyback voltage of 

 the transformers during the interdigit period removes the minority car- 

 riers from both Dl and D2. Since D2 carries a larger current for a longer 

 period than Dl, the carriers are cleared from Dl first. It is then reverse- 

 biased for almost one-half the repetition period before there is any chance 



