1110 THE BELL SYSTEM TECHNICAL JOURNAL, SEPTEMBER 1956 



of false triggering. Hence, diode reverse recovery time is not a problem. 

 However, Dl should have a short forward recovery time in order that : 

 turn-off will occur rapidly. 



One possible limitation of this synchronization method is that a low 

 impedance clock source is necessary. This is usually not difficult to ob- 

 tain with a resonant circuit in the output of the clock signal source. 

 Offsetting this point are the advantages of low clock power, esentially 

 zero standby clock power, only one additional component, and no criti- 

 cal component tolerances. 



7. ILLUSTRATIVE DESIGN 



In the preceding sections the features of various configurations for 

 the functional circuits of an amplifier have been described. The following 

 discussion illustrates the application of these ideas to an amplifier design 

 for use in a digital computer system. It is intended that the descrip- 

 tion of the design philosophy be sufficient to permit its application to 

 other systems. 



In the computer under consideration the amplifier is to be combined 

 with a single level, diode logic circuit to form a logic network. The logic 

 networks, together with delay lines, will be connected in appropriate 

 arrays to perform the logic functions of the sytem, such as addition, 

 multiplication, etc. Digital information is to be represented by one-half 

 microsecond pulses and the amplifiers are to be synchronized at a one 

 megacycle pulse repetition rate by a four phase sine wave master oscil- 

 lator. Other system requirements are mentioned in connection with the 

 selection of the corresponding functional circuit. 



Since the amplifier is considered as a small system of functional cir- 

 cuits, it is necessary, as in most system designs, to re-examine, and pos- 

 sibly change, circuit choices as the design progresses. However, for the 

 sake of clarity, the following discussion omits the re-examination and 

 frequently refers to the final schematic shown in Fig. 13. 



The first step in the design is to select the feedback configuration most 

 suitable to the computer requirements. For this computer the dc and 

 clock power are to be minimized and the amplifier should be able to drive 

 from 1 to 12 logic networks. Miniaturization of the computer implies 

 that there may be an appreciable amount of stray capacity across the 

 amplifier output. These considerations suggest transformer coupled feed- 

 back connected in series with an output circuit. Since both positive and 

 negative output pulses are to be required (one polarity for AND and 

 OM logic and the other polarity for inhil)ition), transformer output cou- 

 pling is indicated. 



